The present invention relates to a network system including a packet switch, and more particularly to a packet network for communication using a virtual channel identifier and a packet switching system which is applied to such a packet network.
In high-speed packet communication represented by broad band ISDN (BISDN), a self-routing switching system has been proposed in which a processing for packet switching is realized by means of hardware in order to improve the transmission throughput in the network. An asynchronous transfer mode (ATM) using a packet having a fixed length is employed in one kind of self-routing switching system. In an ATM network as described in "A DYNAMICALLY CONTROLLABLE ATM TRANSPORT NETWORK BASED ON THE VIRTUAL PATH CONCEPT", GROBECOM '88, 39-2, a plurality of their own virtual path identifiers (VPI's) are multiplexed on one real transmission line and a plurality of logical connections between switching stations having their own virtual channel identifiers (VCI's) are multiplexed on each logical path or VPI, in order to economically use a real transmission line having a high data transmission rate and to transmit a communication packet with an excellent reliability. A logical connection between two terminal units communicating with each other through at least one switching station is identified in each switching station by virtue of the combination of VPI and VCI included in the header portion of a received packet, thereby performing a packet switching operation.
One example of an ATM switch using a self-routing switch developed for application to the ATM network has been reported by, for example, "Asynchronous Transfer Mode Experimental switching System for Broad Band ISDN", Institute of Electronics, Information and Communication Engineers Technical Report, SSE88-29. In the ATM switch according to this Publication, a label conversion unit, having a label conversion table, is placed at the front stage of the self-routing switch so that a reference to the label conversion table is made in accordance with a connection identifier included in the header portion of each received packet to read routing information and a new connection identifier is preliminarily set or written in the label conversion table and is used in the switch, thereby performing the conversion of the label (header) of the received packet. In the above system, however, if VPI and VCI which comprise an identifier for identifying a call are used as an address of the label conversion table as they are, there arises a problem that the capacity of the label conversion table becomes considerably large.
For example, in the case where a line 60 connected to an A station 52 having a virtual path identifier VPI.sub.ac and a line 55 connected to a B station 54 having VPI.sub.bc are multiplexed by a multiplexer 71 in a cross connector 61 so that they are inputted to a relay switch (or C station) 56 through one line 70, as shown in FIG. 1, it is necessary to refer to both VPI and VCI included in the header portion of each received packet in order that the switch 56 identifies a logical connection on the line 70. For example, if the length of a VPI field of the packet header is 12 bits and the length of a VCI field is 16 bits, a label conversion table having an address capacity of 2.sup.28 =256 Mbits is required in the switch 56. This means that the total memory capacity of the label conversion table amounts to the order of G bits. Therefore, it is difficult to realize such a switching network.
Also, in the self-routing switch, it is necessary to preliminarily set routing information RT representive of the output line number of the switch in addition to ordinary packet information for each packet in order to switch an input packet to an output line coincident with a logical connection. In the conventional switch, the addition of the routing information RT gives rise to a problem that the length of a packet in the switch becomes large and hence an improvement in the data processing speed in the switch (or a speed conversion) is required in order to ensure the same throughput at the input and output sides of each switch.